VHDL Implementation in DesignWorks Professional
The DesignWorks Simulator Option now includes ability to create simulation models using the VHDL language. However, DesignWorks does not implement 100% of the VHDL language standard. In order to provide a useful product while still being able to sell it at a reasonable price, we have omitted some of the more advanced features of the language in this version. We have tried to provide a useful set of features that will allow small to medium scale designs to be fully implemented and allow the concepts and exercises in commonly used textbooks to be executed This note lists the language features that have been restricted or omitted.
VHDL Keywords Not Implemented
The language features associated with the following keywords are not implemented:
- ACCESS
- ALIAS
- ATTRIBUTE
- BUFFER
- CONFIGURATION
- DISCONNECT
- FILE
- GENERATE
- GROUP
- LABEL
- NEW
- PORT MAP on BLOCK
- POSTPONED process
- PROTECTED
- REAL
- RECORD
- SHARED
- TRANSPORT/INERTIAL/REJECT
- UNITS
- STABLE QUIET TRANSACTION and DELAYED
Other VHDL Features Not Implemented
In addition, some specific syntactical features, or unusual operations on some data types have not been implemented, including:
- named associations in aggregates
- operator overloading
- extended identifiers
- physical type declaration
- enumerated character type declaration
- user-defined resolution functions
- register types
- inertial delay model
- attributes: only the following attributes are implemented:
- RANGE
- LENGTH
- LEFT
Standard Libraries Supported in DesignWorks
LogicWorks supports only the following standard libraries:
- SYSTEM
- STD_LOGIC_1164 - subtypes X01, X01Z, UX01 and UX01Z are not implemented
- STD_LOGIC_ARITH
The above packages are hardwired into the compiler for maximum speed and compactness. In general, other packages cannot be used without some massaging because the standard source code uses VHDL features that are not yet implement in DesignWorks.
Other Implementation Notes
Compilation Units
The VHDL compiler in LogicWorks will only accept a single ENTITY/ARCHITECTURE pair or PACKAGE/PACKAGE BODY pair per file.
Signal Values in VHDL Simulations
When you compile a VHDL file in LogicWorks, the program actually generates a structural circuit consisting of the various blocks described in the code. Each process (including signal assignments or other constructs that create an implicit process) creates a device with signal inputs and outputs. The existing LogicWorks simulator simulates the signal interconnections between these process blocks. This gives considerable flexibility in interconnecting structural and VHDL components, but places some restrictions on signal values, including:
- Signals declared in VHDL can only be bit, std_logic, boolean or integer types or 1-dimensional arrays of bit, std_logic or boolean.
- Signals are always resolved and use the DesignWorks simulator’s resolving algorithm. Non-resolved types can be declared but are always implemented as resolved. User-defined resolution functions are not supported.
- The ‘inertial’ delay specification is ignored.
- The ‘register’ designation on a signal is ignored.
